In a master-slave flip-flop, the master and slave latches are transparent on complementary clock states. For example the master latch may be configured to be transparent (and thus able to latch the incoming data) when the clock is high. The master is then closed when the clock is low. Similarly, the slave latch may be configured to be transparent when the clock is low and closed when the clock is high. Alternatively, the master latch may be configured to transparent when the clock is low whereas the slave latch would then be transparent when the clock is high. In one clock cycle, the master latch thus captures the data on a first clock edge that is then latched by the slave latch in a subsequent second clock edge in the same clocking period. In a serial chain of such flip-flops, the data output from a slave latch in one flip-flop is the data input to the master latch in a subsequent flip-flop. A data bit latched in one flip-flop during a first clock cycle is thus latched in a subsequent flip-flop in a subsequent second clock cycle.
During relatively low-speed operation, the transfer from one flip-flop to a subsequent flip-flop is relatively straightforward as the relatively slow clocking speed provides ample setup timing margins in the timing path coupling the flip-flops. But in a high-speed design, the increased clocking speed makes it difficult for the subsequent flip-flop to capture its data at the clock-triggering edge because the setup time of the flip-flop together with the data propagation delay in the timing path between the flip-flops may approach or exceed the clock cycle period. Moreover, clock jitter reduces the effective time available in the clock cycle for data propagation and setup time. If the jitter, data propagation delay, and setup time together are longer than the clock cycle, the incoming data value will not be properly captured by the subsequent flip-flop. This erroneous operation is denoted as a setup timing failure.
To provide more robust high-speed performance despite clock jitter, it is thus known to provide a flip-flop in which the clocking of the master latch is delayed with respect to the clocking of the slave latch. The delayed clock to the master latch provides sufficient setup margin despite the existence of clock jitter such that the resulting flip-flop may be designated as “jitter-tolerant” (JT) flip-flop. As a result, setup margin (the required minimum amount of setup time) for the JT flip-flop may be reduced although this comes at the cost of an increased hold margin (the required minimum amount of hold time). Although a JT flip-flop is thus robust to clock jitter, the delayed clock to the master latch may cause errors during scan chain formation in the test or scan mode of operation. As known in the test arts (e.g., JTAG), a circuit may be tested by sequentially shifting in a scan-in test vector so that a resulting scan-out vector may be shifted out to determine the presence of circuit errors or defects. But the increased hold margin requirement for the JT flip-flop may result in hold violation during scan mode.
During normal operation, the increased hold margin is not an issue due to the processing delay provided by the logic circuitry coupled between adjacent flip-flops on a timing path. The logic circuitry processes the Q signal from an initial flip-flop into a logic output signal that in turn is re-latched in the subsequent flip-flop on the timing path. The logic circuitry processing provides sufficient delay so that no hold time violations occur. But a scan path has no intervening logic from one JT flip-flop to the next flip-flop in the scan path. The connecting scan paths are fairly short in that the successive JT flip-flops in the scan chain tend to be relatively adjacent to one another on the die. Just like conventional flip-flops, each JT flip-flop would include an input multiplexer that selects between the data input and the scan-in input signal. In normal operation, the input multiplexer selects for the data input signal. However, in scan mode the input multiplexer selects for the scan-in input signal. In a scan chain of JT flip-flops (which may also be denoted as high-speed flip-flops), the input multiplexers are relatively fast such that they cannot provide sufficient delay to prevent the occurrence of hold violations. In particular, a scan-in bit may pass through one JT flip-flop in the scan chain and be registered in the successive JT flip-flop on the same clock edge because of the insufficient hold margin issue. This is plainly undesirable as the successive JT flip-flop is supposed to register its corresponding scan-in signal, not the scan-in signal intended for the preceding JT flip-flop in the scan chain.
Accordingly, there is a need in the art for high-speed flip-flops that retain their jitter tolerant performance during normal operation but are robust to hold scan mode hold violations.